where we are: a complete adder, end-to-end
Chain four of the full adders from the previous page. Each carry-out feeds the next carry-in. You can now add two 4-bit binary numbers and get a 5-bit result. This is a complete arithmetic circuit, end-to-end.
Real CPUs use 32 or 64 bits per number; the only difference is more FAs in the chain. The pattern — chain of bit-slices, carries propagating LSB → MSB — is what every CPU's integer add ultimately runs.
FA0 at the bottom (LSB), FA3 at the top (MSB). Each FA's A and B inputs come in from the LEFT; each S exits to the RIGHT; the carry chain (C01, C12, C23) climbs LSB → MSB on the right side. Type two 4-bit numbers using A and B, then watch the carry ripple up.
0 + 0 = 0
Hit ↺ reset. All inputs 0. Everything dark. Display reads 0 + 0 = 00000.
Each FA sees (A=0, B=0, Cin=0) → all outputs 0. No carry generated anywhere.
1 + 1 = 0010 — the smallest carry
Click A0 and B0. A = 0001, B = 0001.
FA0 sees A0=1, B0=1, Cin=0 — the "both inputs high" case from the full adder page. S0=0, but a carry is generated. C01 lights up.
FA1 receives that carry. A1=0, B1=0, Cin=1 — exactly one input is high, so S1=1, no further carry. The result: 0010 = 2.
FA2 and FA3 stay dark — the carry never reached them.
5 + 3 = 1000 — multi-stage ripple
Set A = 0101 (A2, A0) and B = 0011 (B1, B0). A is 5, B is 3.
FA0: 1+1+0 = 10. S0=0, C01 fires.
FA1: 0+1+1 = 10. S1=0, C12 fires.
FA2: 1+0+1 = 10. S2=0, C23 fires.
FA3: 0+0+1 = 1. S3=1, no Cout.
Result: 1000 = 8. Three carries in a row — the carry "rippled" all the way up from FA0 to FA3.
15 + 1 = 10000 — max overflow
Set A = 1111 (all four A buttons) and B = 0001. A is decimal 15, the maximum 4-bit value.
Adding just 1 forces a carry at every position: every FA receives sum1=1 and Cin=1 (after the first), so every FA's c2 fires (or its c1, depending). Every internal carry wire — C01, C12, C23 — lights up, and finally Cout = 1.
The result is 5 bits: 10000 = 16. We've overflowed the 4-bit range. Cout is how a 4-bit adder tells you the sum didn't fit.
the ripple delay
FA3's S depends on the carry from FA2, which depends on FA1's carry, which depends on FA0's. The bits are computed in sequence, not in parallel.
In real silicon each FA takes ~50-100 picoseconds to settle. The worst-case delay of an N-bit ripple adder is N×, so a 64-bit one would be very slow. That's why modern CPUs use carry-lookahead or carry-save adders. But the underlying logic is what you see above.
why this matters
This is integer addition. Every add instruction in every CPU ultimately runs a circuit shaped like this — typically 32 or 64 bits wide. Subtract reuses the same circuit (B inverted plus Cin=1, two's complement). Multiply is repeated addition. Comparisons are subtraction with the carry inspected.
Combined with the register from earlier and a clock, four full adders is enough to build a complete, programmable arithmetic machine.