where we are: adding a door
The SR latch can store a bit, but its interface is clumsy — separate set/reset commands and a "forbidden" input combination that breaks it. This page wraps it in a gating circuit that exposes a clean API: one data input (D), one control input (EN).
This is the first cell with separate data and control lines. The "clock" idea starts here. EN=1 means "listen to D"; EN=0 means "hold what you have." Every clocked CPU register follows this pattern.
An inverter, two gating NANDs (G_S, G_R), and an SR latch — now demoted to a building block. Toggle D and EN to see when the cell is deaf and when it's listening.
EN = 0 (door closed)
Hit ↺ reset. Click D a few times. Q doesn't move.
Look at G_S and G_R: both glow. By the NAND rule, any 0 forces the output to 1. EN=0 feeds that 0 to both gating NANDs, so both output 1 no matter what D does. And both S̄=R̄=1 is the SR latch's HOLD command. The cell is deaf.
click EN → 1 (door opens)
Now the NAND rule has nothing forcing the outputs — they start computing. G_S outputs NAND(D, EN) = NOT D, G_R (fed by the inverter) outputs NAND(!D, EN) = D. Whatever D is, one of S̄/R̄ will be 0 and the other 1, and the SR latch snaps to match. Q now equals D.
wiggle D (transparent mode)
Click D back and forth. Q follows you. This is transparent mode: while the door is open, the output is a delayed echo of the input. There's no memory yet — it's a wire with a small delay.
Hover G_S, G_R, or the SR latch to see their interiors update in real time.
EN → 0 (door closes)
Whatever D was at the instant you released EN is now locked in. Q freezes. Wiggle D — nothing happens. The cell has captured.
Both gating NANDs went back to outputting 1, putting the SR latch in HOLD. The bit is being remembered by the same cross-coupled loop as before; the gating NANDs just decide when to deliver new inputs.
the trick that makes it work
It all rests on one fact: NAND with any 0 input is forced to 1. EN=0 makes both gating NANDs output 1, which is the SR latch's HOLD command. EN=0 doesn't tell the cell "don't change" — it tells the gating NANDs to shout 1 at both S̄ and R̄.
The inverter on D guarantees one of S̄/R̄ is 0 and the other 1 when EN=1, so the forbidden state (both 0) is structurally impossible. The D latch is the SR latch made safe.
why this matters
This is the first cell with a control input separate from data. The "clock" concept is born here. Everything downstream — registers, pipelines, the entire synchronous discipline of CPU design — rests on the idea that a control signal decides when data is captured.
The catch: while EN is held high, Q just tracks D. The next layer (D flip-flop) fixes that with edge-triggered capture.