where we are: many bits in lockstep
A single DFF stores one bit — useful for yes/no. But wire N of them in parallel sharing the same CLK, and you can store an N-bit number that all updates as one atomic unit.
This is a register — named storage. Give it a name (x1, x2, pc) and you have what a CPU calls a register. RISC-V has 32 of these, each 32 bits wide — a thousand DFF cells exactly like the ones on this page, all sharing the chip's master clock.
Four DFFs (bit 0 at top, bit 3 at bottom), each with its own D input and Q output, all wired to one CLK. Press pulse CLK 0→1→0 — all four capture in the same rising edge.
CLK = 0 — masters loading
Hit ↺ reset. All Ds are 0, CLK is 0, all Qs are 0. Now flip a few D buttons — say D0 and D2 to 1. None of the Q pins move.
The four masters are each independently soaking up their D input, but the slaves are all holding (their EN = CLK = 0). The bit pattern is "queued up" inside the masters, waiting for permission to advance.
pulse the clock
Hit pulse CLK 0→1→0. Watch carefully. CLK rises, and all four output pins update at the same moment. The bits queued in the masters transfer to the slaves simultaneously. The stored word display shows the new value.
Notice nothing happened gradually. No "bit 0 updated, then bit 1, then bit 2." All four flipped on the same edge.
independence + atomicity
Try wiggling the Ds while CLK = 1 — none of the Qs change, exactly like in the standalone DFF page. Each cell, taken alone, is doing nothing surprising.
What's new is the global property: because every cell shares the same CLK wire, the moment of capture is shared too. The whole register snapshots its inputs in one indivisible instant.
the magic of the shared clock
Each DFF, alone, converts a level into a moment. The deeper magic shows up only when you wire many to the same clock. Suddenly N bits captured on different physical cells become a single logical value that updates atomically.
That property is what lets us treat the 4-bit pattern as a number. Without atomicity, "the register" wouldn't have a well-defined value at any instant. With atomicity, it does.
why this matters
This is the substrate of a CPU. RISC-V has 32 general-purpose registers, each 32 bits — that's 1024 cells exactly like these, all sharing the chip's master clock. Every instruction either reads from or writes to one of these registers, and writes happen at rising clock edges.
Pipelines, register files, state machines all rest on this one trick: connect many flip-flops to a shared clock and you get atomic, synchronous, multi-bit memory.