where we are: turning a level into an instant
The D latch captures D while EN is held high — a duration. But most CPUs need a precise moment, a single instant when all state updates atomically. This page builds that.
Stack two D latches with opposing enables — master open when CLK=0, slave open when CLK=1 — and you get a cell that captures D only at the exact moment the clock rises. We've turned a level into an event. This is called a flip-flop, the storage element in every clocked digital system.
Master on the left, slave on the right, inverter on the CLK. Press pulse CLK 0→1→0 to trigger one clock cycle and watch the bit travel master → slave at the rising edge.
CLK = 0 (master is open)
Hit ↺ reset. CLK is 0. The !CLK wire glows (master's EN=1, transparent). The CLK wire is dark (slave's EN=0, holding).
Click D a few times. The master body and M wire follow D. But Q does not move. The master is loading; the slave's door is closed.
CLK 0 → 1 — the rising edge
Click CLK (or pulse CLK 0→1→0). Two things happen in the same instant:
• The master door slams shut. Whatever was on M is now frozen.
• The slave door opens, sees the frozen M, propagates to Q.
The output moves. Exactly when it moves: at the moment the clock rose. Not while it's high — at the boundary itself.
CLK = 1 (slave open, master locked)
Click D back and forth while CLK is 1. Q does not change. The master's door is shut, so D can wiggle all it wants. The slave is transparent but only echoes the frozen M.
You've decoupled the data input from the output between rising edges.
CLK 1 → 0 — the falling edge
Click CLK. Falls back to 0. Slave's door shuts; master's door reopens. Wiggling D updates M, but Q stays frozen at the last rising-edge value.
While CLK is low, master loads the next value; slave holds the previous. On the next rising edge they swap roles. The two halves take turns.
the magic moment
The whole behavior is: master enabled when CLK=0, slave enabled when CLK=1, instantaneous handoff at the edge. A value can only travel D → master → slave → Q at the precise instant the clock rises — an instant with no duration.
We've converted a level into an event. That's what makes this a flip-flop and not a latch.
the second output: Q̄ — where it matters, where it doesn't
The slave is an SR latch, and SR latches physically produce two complementary outputs: Q and Q̄ (Q-bar, always the inverse of Q). It's not a design choice — the cross-coupled NANDs at the core of the SR latch make both at once, for free. That's why this page draws two output wires.
At higher abstraction levels we'll mostly ignore Q̄. The register on the next layer up only takes Q from each DFF. Same for the program counter, ALU, and pipeline latches in a CPU datapath — they consume Q and let Q̄ float, unused.
But Q̄ is load-bearing in a few important places: SRAM (every cache bit cell reads bit and bit̄ together into a differential sense amp, much faster and more noise-tolerant than reading bit alone), DRAM (same trick), high-speed I/O like DDR / PCIe / USB 3 (transmits data as a complementary D+ / D− pair), and toggle flip-flops built by feeding Q̄ back into D (the classic way to build ripple counters and clock dividers).
Modern synchronous CPUs avoid toggle flip-flops in favor of register-plus-adder counters (which is what we'll build next on the PC page) — so Q̄ disappears from the architectural view above this layer, even though it's still doing work down in the cache and the I/O.
why this matters
Every flip-flop on a chip shares one clock wire. On each rising edge, all of them snapshot their inputs simultaneously and atomically — the entire machine steps forward in one synchronized heartbeat.
The "rising edge" is the basic unit of time in a digital machine. And it comes for free from cross-coupling two level-triggered latches with opposing enables.